作者: Richard W. Arnold , Reynaldo M. Rincon
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摘要: A probe card assemblage for simultaneously testing one or more integrated circuit chips including an interposer having on surface a plurality of protruding contact elements electrically contacting wafer positioned atop layer compliant material, and arrayed in pattern corresponding to chip pads, series conductive vias through the insulating which connect with arrangement leads terminating universal connectors second surface, mating those interposer. The is secured are card, thereby providing vertical makes use ultrasonic energy minimize scrub over travel. specific tester configuration common family circuits be tested.