作者: Hiroshi Miyamoto , Kazutami Arimoto , Shigeru Mori , Tadato Yamagata , Michihiro Yamada
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摘要: An internal power supply voltage generator for generating an a semiconductor integrated device includes first and second reference generators which produce voltages having respective values predetermined amount above below optimal value of the voltage. The are constructed pair serially connected NMOS PMOS transistors, respectively, transistors between external ground. applied to CMOS output stage transistor ground, gates being coupled voltages, so as provide said at common node transistors. This exhibits lowered dissipation impedance, result providing stage.