Processor instruction cache with dual-read modes
作者： Jason Sheu , Jason T. Su , Jensen Tjeng , Hong-Yi Chen , Sehat Sutardja
DOI:
关键词:
摘要: A processor includes a cache memory. The memory an array of cells, word lines and bit lines. control module enables line the to access first cell in enabled line. disables maintains disabled state second
google.it 参考文章(11)
Rene P. Helbing, Stephen A. DiCarolis, Ronald Hiskes, Growth of electroluminescent phosphors by MOCVD ,(1996)
David J. Mayer, Mark E. Taylor, Paul R. Culley, Improved paged memory controller ,(1990)
Randal Lee Guck, Selective multiple protocol transport and dynamic format conversion in a multi-user network ,(1996)
Michael Scott McIlvaine, James Norris Dieffenderfer, Victor Roberts Augsburg, Rodney Wayne Smith, Jeffrey Todd Bridges, Thomas Andrew Sartorius, Power Efficient Instruction Prefetch Mechanism ,(2006)
Gi Ho Park, Branch target buffer and method of use ,(2008)
Franck Sala, Eran Altshuler, Tal Gat, System, method and device for queuing branch predictions ,(2003)
Nobuhiro Maki, Masamitsu Takahashi, Katsuhisa Miyata, Masahide Sato, Computer system, management method and storage network system ,(2005)
Satoshi Nakazato, Multiport cache memory and access control system of multiport cache memory ,(2005)
Katsunori Seno, Bitline precharge halt access mode for low power operation of a memory device ,(1996)
Edward Grochowski, John Shen, Hong Wang, Alejandro Ramirez, Cache-line reuse-buffer ,(2002)