Analog-digital converter

摘要: Two A-D converters which provide different embodiments of the general successive rectification algorithm Vout = 2|Vin| - Vref. One stage a synchronous parallel converter generally comprises comparator (32), and an op amp (35) with Vin as input to its inverting input, noninverting connected ground, output being Vout, first capacitor (C1) bridging inputs amp, second (C2) half capacitance feeding back from input. Each stage's is compared ground bit information. continuous complementary transistor pair (M1, M2) three current mirrors (70, 75, 80). The pair, mirror (70) (75) act rectifier. third (80) acts subtract Iref rectified amplified Vin, has Vref Iout. Iout one Iin stage, stages are cascaded. direction flow each provides bits