作者: Masaki Ichihara
DOI:
关键词:
摘要: In an analog-to-digital converter, one-bit A/D conversion stages are connected in series to receive analog signal. Each stage includes a sample-and-hold circuit for sampling signal from preceding stage, comparator comparing it with specified voltage level produce logic at one of two discrete levels depending on whether the received is higher or lower than level. The summed prescribed reference opposite polarities output successive driven so that each transferred next, and signals generated by individual delayed they appear simultaneously digital terminals.