Parallel/serial scan system for testing logic circuits

摘要: A testable logic circuit includes parallel registers (72)-(80) for interfacing with a common internal bus (70). The are individually addressable by an address decoder (104) storage of test vectors therein. These then applied to associated circuits. Individual shift register latches (92)-(102) provided at imbedded locations interfaced serial data link allow loading function in both the mode store application and also operational data. Use increases speed which is scanned into device.