Post-Production Test Strategies for Approximation Circuits

作者: Arun Chandrasekharan , Daniel Große , Rolf Drechsler , Arun Chandrasekharan , Daniel Große

DOI: 10.1007/978-3-319-98965-5_6

关键词:

摘要: Post-production test or simply is the process of sorting out defective chips from proper ones after fabrication. This chapter examines impact approximations in post-production and proposes methodologies that have potential for significant yield improvement. To best our knowledge, this first systematic approach considering design level test.

参考文章(15)
Wang Ling Goh, Kiat Seng Yeo, Ning Zhu, An enhanced low-power high-speed Adder For Error-Tolerant application Proceedings of the 2009 12th International Symposium on Integrated Circuits. pp. 69- 72 ,(2009)
Bernd Becker, Rolf Drechsler, Stephan Eggersgluss, Matthias Sauer, Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization international conference on design and technology of integrated systems in nanoscale era. pp. 1- 10 ,(2014) , 10.1109/DTIS.2014.6850674
Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer, Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 31, pp. 754- 764 ,(2012) , 10.1109/TCAD.2011.2179036
Muhammad Shafique, Waqas Ahmad, Rehan Hafiz, Jörg Henkel, A low latency generic accuracy configurable adder design automation conference. pp. 86- ,(2015) , 10.1145/2744769.2744778
Andrew B. Kahng, Seokhyeong Kang, Accuracy-configurable adder for approximate arithmetic designs Proceedings of the 49th Annual Design Automation Conference on - DAC '12. pp. 820- 825 ,(2012) , 10.1145/2228360.2228509
Rong Ye, Feng Yuan, Ting Wang, Qiang Xu, Rakesh Kumar, On reconfiguration-oriented approximate adder design and its application international conference on computer aided design. pp. 48- 54 ,(2013) , 10.5555/2561828.2561838
Suraj Sindia, Vishwani D. Agrawal, Tailoring Tests for Functional Binning of Integrated Circuits asian test symposium. pp. 95- 100 ,(2012) , 10.1109/ATS.2012.78
M.C. Hansen, H. Yalcin, J.P. Hayes, Unveiling the ISCAS-85 benchmarks: a case study in reverse engineering IEEE Design & Test of Computers. ,vol. 16, pp. 72- 80 ,(1999) , 10.1109/54.785838
Kuen-Jong Lee, Tong-Yu Hsieh, M.A. Breuer, A novel test methodology based on error-rate to support error-tolerance international test conference. pp. 9- ,(2005) , 10.1109/TEST.2005.1584081
Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue, A Practical Approach to Threshold Test Generation for Error Tolerant Circuits asian test symposium. pp. 171- 176 ,(2009) , 10.1109/ATS.2009.19