Accelerating coverage convergence using symbolic properties

摘要: In a method for increasing coverage convergence during verification of design an integrated circuit, multiple simulation runs can be performed. Symbolic variables and symbolic expressions generated the variable in hardware code test bench. Exemplary include description language (HDL) and/or (HVL) code. properties, which are derived from propagating through bench runs, collected. Coverage information analyzed to identify points targeted. At this point, each identified constraints resulting collected properties solved generate directed stimuli design. These increase convergence.