Scan chain verification using symbolic simulation
作者： Padmaraj Sanjeevarao , Harinath B. Kamepalli , Chang-Jin Park
DOI:
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摘要: A method and apparatus for improved formal scan chain equivalence checking to verify the operation of components in a VLSI integrated circuit is described connection with using symbolic simulation verification equivalency between different modeling representations circuit-under-test. The present invention enhances previous techniques by loading each scannable state-element design expression that characterizes logical location element performing shift contents at scan-out other primary output pins design.
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