Improving Diagnosis Efficiency via Machine Learning

摘要: Logic diagnosis, the process of identifying and locating possible defects in failing integrated circuits, is a key step yield learning for both technology development high-volume manufacturing. However, resources can be easily wasted if diagnosis results no meaningful information, or type diagnostic result not actionable. It would therefore very beneficial to have comprehensive preview outcomes beforehand, which allows prioritized more reasonable effective way. In this work, methodology developed predict whether fail log given design will outcome that purpose at hand. Specifically, aim time required produces any defect candidates, so, are those candidates logic failure chain failure. Random Forest classification algorithm used prediction. Experiments on 28nm test chip 90nm part illustrate provide accurate prediction (0.95+ precision, 0.9+ recall F1-score, 0.96+ AUC average) when two classes balanced, satisfactory 0.98+ imbalanced.