LORAx: A High-speed Energy-efficient Lower-Order Rounding-based Approximate Multiplier

摘要: Applications such as image, audio, and video processing are tolerant to certain amounts of error. This tolerance/resiliency can be exploited construct approximate circuits with improved design parameters area, power, delay. paper presents a high-speed yet energy-efficient multiplier for low-power applications. In the proposed scheme, operands divided into accurate (significant) rounded (insignificant) sections at half operand bit-length. Further, simplified multiplication operations performed between these obtain final product. The architecture involves an small width well shifter blocks, which leads delay- architecture. performance over existing is evaluated by coding designs in Verilog implementing on Artix7 family XC7A100TCSG324 FPGA device using Xilinx ISE tool chain. simulation results show 23–31% up 26% delay energy savings, respectively, architectures.