Yet Another Silicon Compiler

摘要: In this paper, we describe the YASC high-level silicon compiler which synthesizes compact chip layouts from hierarchical behavioral descriptions. A logic synthesis procedure generates sets of Boolean equations, including multi-phase clocks and any necessary interface logic. novel technique for layout generation yields cells whose densities approach hand-crafted designs. Two-layer metal NMOS CMOS technologies are supported, with flexible design rules. addition to synthesis, logic, schematic graph diagrams generated directly a powerful internal data base. The compiler, runs under UNIX^^ operating system, includes menu-driven multi-windowing user environment.