Method of fabricating a wafer level chip scale package without an encapsulated via

作者: Andrew Holland

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摘要: An improved wafer level chip scale packaging technique is described which does not use an encapsulated via to connect between a redirection layer and pad within the ring on semiconductor die. In embodiment, first dielectric formed such that it terminates each die die's ring. Tracks are then in conductive contact one of pads run over edge opening onto surface layer. These tracks may be used form electrical connection solder ball.