Logic gate having an isolation FET and noise immunity circuit
作者： Jr. Richard B. Watson
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摘要: A field effect transistor (FET) logic gate wherein a plurality of FETs is coupled to an output enhancement mode FET through noise immunity circuit, such circuit including Schottky diode. biasing network ensures that any conducting one the input transistors produces forward voltage drop between its and less than diode ensuring at electrode threshold in presence noise. In embodiment includes coupling having source transistors. first current thereby provides sufficient drive into full conduction when are low states. second drain supplies predetermined amount one, or ones, The supplied by determined accordance with fan-out requirements independent bias provided place conduction.
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