Input-voltage detector circuit for CMOS integrated circuit

摘要: An input-voltage detector circuit for increasing the functionality of a CMOS integrated without requiring an increase in number pins or terminals includes N-channel enhancement-mode transistor having its source terminal and substrate region electrically connected to input circuit. A ground-voltage potential is applied gate load element between drain positive-voltage power supply node The further buffer stage which provides output detects when voltage more negative than ground by predetermined level Thus, provided application unusual condition at input; can be utilized other on-chip logic cause function differently under usual conditions.