High speed logic and memory family using ring segment buffer

摘要: A logic and memory family using CMOS technology operates at high speeds a Ring Segment Buffer to couple gates one another in an integrated circuit chip, cells other circuits provide shift registers, triggers, clock pulse generators related circuits. The comprises or more serially connected complementary field effect transistor (FET) inverter stages, with the output of preceding stage being input succeeding stage. N-channel FET each has channel width which is less than predetermined factor (K) times immediately By maintaining K relationship, can drive large capacitive loads speed. may also delay function length number stages. For loads, last be replaced by bipolar transistor-FET driver minority carrier lifetime controlled transistors are used. Cell Logic Delay Storage present invention operate 300 megahertz conventional semiconductor fabrication processes 70 less. fourfold speed improvement thereby obtained.