Interactive presentation: Functional and timing validation of partially bypassed processor pipelines

摘要: Customizing the bypasses in pipelined processors is an effective and popular means to perform power, performance complexity trade-offs embedded systems. However existing techniques are unable automatically generate test patterns functionally validate a partially bypassed processor. Manually specifying directed sequences processor not only complex cumbersome task, but also highly error-prone. In this paper we present automatic generation technique verify pipeline using high-level description. We define fault model coverage metric for demonstrate that our can fully cover all faults 107, 074 tests Intel XScale within 40 minutes. contrast, randomly generated achieve 100% with 2 million after half day. Furthermore, able possible bypass configurations of