An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation

摘要: Design validation is becoming more and a bottleneck in the microprocessor design process. The difficulty of stems from complexity design, which requires searching an enormous space to check correctness. This exacerbated by features for enhancing performance, such as pipelines, are common most microprocessors. paper describes new abstraction technique handle this problem. Our solution novel method identify control states automatically processor HDL description extract abstract finite state machine model preserves behaviors accurate clock cycle, so that be analyzed drastically reduced. This used evaluate microarchitecture-level coverage tests. We also present test generation algorithm traversing transition paths covering snapshot temporal events. These with length, along information about instruction set, generate system-level Results on example models show efficient finding bugs other verification methods miss.