作者: Pritish R. Parida , Augusto Vega , Alper Buyuktosunoglu , Pradip Bose , Timothy Chainer
DOI: 10.1109/ITHERM.2016.7517567
关键词:
摘要: High-end server-class processors continue to push towards increased performance in both single thread and throughput performance. Improved computational power efficiency can be achieved by increasing the number of complex cores through three-dimensional (3D) chip stacking technology. However, thermal associated reliability issues a limiting factor such strategy unless it is augmented an aggressive, new cooling solution. This research paper demonstrates novel intrachip two-phase liquid technology with channel dimensions which are consistent silicon vias (TSV) compatible 3D mitigate any constraints. To evaluate benefits, data from characterization studies IBM POWER7+™ systems corresponding microprocessor maps were used generate models. These models combined system-level perform quantitative analysis on system