N channel JFET based digital logic gate structure

摘要: A circuit topography is presented which used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has application state art in high temperature, for example 300° C. 500° higher, silicon carbide (SiC) device production. The ability produce inverting combinatorial enables production pulse edge triggered latches. scale synthesis would bring machine capabilities devices operating extremely hot environments, such as surface Venus, near hydrothermal vents, within nuclear reactors (SiC inherently radiation hardened), internal combustion engines. basic gate can be configured a driver oscillator circuits allowing time bases simple digitizers resistive or reactive sensors. structure this innovation, inverter, reconfigured into various analog topographies through use feedback structures.