作者: Xiaoju Wu , Joe Trogolo , Flex Inoue , Zhenwu Chen , Pam Jones-Williams
DOI: 10.1109/ICMTS.2007.374457
关键词:
摘要: In this paper, we report detailed studies on the impacts of sinter process and metal coverage CMOS transistor matching parameter variability in an analog technology. Transistor variations with different slotting sizes processed at temperatures have also been studied. It has found that both plating temperature play critical roles variation. Metal degrades VT current (VT offset ~30 mV, DeltaI/I~18% moderate inversion DeltaI/I~3% strong inversion) significantly low temperature. array size 15umX15um 5um separation over demonstrated to be very effective reducing systematic mismatching. The mismatching improves higher Calculated agree well experimental results.