作者: Loïc Lagadec , Bernard Pottier , Damien Picard
DOI: 10.1016/J.MEJO.2009.02.001
关键词:
摘要: Contrasting with the extensive research focusing on nano-devices properties and fabrication, not enough attention is probably given to computing architectures for these devices. This paper describes a method mapping an FPGA architecture nano-device called NASIC (for Nano-ASIC). illustration of interest nano- micro-architecture models stacked quickly obtain CAD environments investigated technologies.