Priority requestor accelerator

摘要: A system for accelerating the granting of prioritized memory requests to a multi port data processing is disclosed. The priority requestor accelerator detects fact that one remaining in system. logic cleared out before end normal cycle. This allows acceptance new set requestors be presented circuits at time rather than waiting until presentation final request. Thus, from previous requesting snap are on their last preclearance lower ranks as circuit finishes its then loaded and inputs snapped shut beginning cycles. overall operation happens if just moving another already residence after snap. Without this acceleration, full cycle would have been lost with each reloading register.