System for controlling access to computer bus having address phase and data phase by prolonging the generation of request signal

摘要: A computing system is disclosed which uses a busy signal on its bus to help control access said bus. One or more requesters can generate request when the not asserted. System asserted along with signal(s) and remains until all generated have gained in order of priority. freeze during address phase an instruction wait each data transfer instruction. The may be by memory unit, module requester.