A 36/72b CMOS micro-mainframe chip set
作者： D. Fier , R. Caulk , P. Torgerson , D. Breid , R. Bradley
DOI: 10.1109/ISSCC.1986.1156955
关键词:
摘要: A six-chip processor set with mainframe compatible instructions, containing 786,000 transistors, fabricated a 1.2/μ m double-layer metal technology, will be described. The chip can configured to operate from 0.4 1.5MIPS.
sci-hub.se 参考文章(1)
N.E. Preckshot, S.A. Campbell, W.W. Heikkila, D. Dokos, R.H. Passow, W.N. Grant, D. Schultz, J.P. Victorey, Design methodology of a 1.2-µm double-level-metal CMOS technology IEEE Transactions on Electron Devices. ,vol. 31, pp. 215- 225 ,(1984) , 10.1109/T-ED.1984.21504