THE OPTIMAL NUMBER AND LOCATION OF GROUNDED VIAS TO REDUCE CROSSTALK

作者: Wen-Tzeng Huang , Chi-Hao Lu , Ding-Bing Lin

DOI: 10.2528/PIER09071709

关键词:

摘要: Modern electronic products are increasingly based on high-speed, high-density circuitry operating at lower voltages. With such designs, the signal integrity (SI) in a poor printed circuit board layout is afiected by noise and may become unstable. Crosstalk major source of that interferes with SI. Generally, crosstalk can be reduced adding guard trace between victim aggressor areas circuit. In addition, grounded vias added to help reduce crosstalk. Since large number degrade SI ∞exibility routing, we propose method calculate optimal distance determine smallest required achieve performance reducing We show time-domain simulation our reduces near- end 27.65% far-end more than 31.63% compared three-width rule. This backed up experimental results not only reductions 34.49% 37.55% for over time-domain, respectively, but also 2.1dB 3.3dB frequency-domain, respectively. Our indicate has better other methods.

参考文章(13)
H. Sobol, Applications of integrated circuit technology to microwave frequencies Proceedings of the IEEE. ,vol. 59, pp. 1200- 1211 ,(1971) , 10.1109/PROC.1971.8365
M.S. Sharawi, Practical issues in high speed PCB design IEEE Potentials. ,vol. 23, pp. 24- 27 ,(2004) , 10.1109/MP.2004.1289994
I. Novak, B. Eged, L. Hatvani, Measurement and simulation of crosstalk reduction by discrete discontinuities along coupled PCB traces IEEE Transactions on Instrumentation and Measurement. ,vol. 43, pp. 170- 175 ,(1994) , 10.1109/19.293415
A. Suntives, A. Khajooeizadeh, R. Abhari, Using via fences for crosstalk reduction in PCB circuits international symposium on electromagnetic compatibility. ,vol. 1, pp. 34- 37 ,(2006) , 10.1109/ISEMC.2006.1706258
Kyoungho Lee, Hyun-Bae Lee, Hae-Kang Jung, Jae-Yoon Sim, Hong-June Park, A Serpentine Guard Trace to Reduce the Far-End Crosstalk Voltage and the Crosstalk Induced Timing Jitter of Parallel Microstrip Lines IEEE Transactions on Advanced Packaging. ,vol. 31, pp. 809- 817 ,(2008) , 10.1109/TADVP.2008.924226
I. Novak, B. Eged, L. Hatvani, Measurement by vector-network analyzer and simulation of crosstalk reduction on printed circuit boards with additional center traces instrumentation and measurement technology conference. pp. 269- 274 ,(1993) , 10.1109/IMTC.1993.382637
Yung-Shou Cheng, Wei-Da Guo, Guang-Hwa Shiue, Hung-Hsiang Cheng, Chen-Chao Wang, Ruey-Beei Wu, Fewest vias design for microstrip guard trace by using overlying dielectric electrical performance of electronic packaging. pp. 321- 324 ,(2008) , 10.1109/EPEP.2008.4675945
Daniele Rossi, Paolo Angelini, Cecilia Metra, Giovanni Campardo, Gianpietro Vanalli, Risks for Signal Integrity in System in Package and Possible Remedies european test symposium. pp. 165- 170 ,(2008) , 10.1109/ETS.2008.23