A reconfigurable logic-based processor for the SCAN image and video encryption algorithm
作者： C. Kachris , N. Bourbakis , A. Dollas
DOI: 10.1023/B:IJPP.0000004512.53221.FF
关键词:
摘要: This paper presents a detailed architecture and reconfigurable logic based hardware design of the SCAN algorithm. can be used to encrypt high resolution images in real-time. Although algorithm is block cipher with arbitrarily large blocks, present for 64 × pixel blocks order provide real-time image encryption throughput. The was initially targeted at Xilinx XCV-1000 FPGA, which performance results are presented paper.
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