作者: EA Fitzgerald , KE Lee , SF Yoon , SJ Chua , CS Tan
DOI: 10.1109/EDSSC.2015.7285034
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摘要: The incorporation of new materials into CMOS scaling has become a necessity. Our previous work in SiGe and III-V integration shows promise allowing further for increased transistor density. However, principal concern is that investment returns by increasing density will likely be negative all but possibly one or two corporations, may all. innovation incorporating other monolithically silicon now leading us pre-paradigm age which metrics at the device level are not sufficient to determine innovative value CMOS+X combinations marketplace. Such an is, definition, challenge organizations participating paradigm: research organizations, government funding agencies, public private corporations. Despite these challenging times, we list characteristics path, describe our efforts follow it through ‘white space’ integrated circuits employing devices. Initially, designing novel circuits, processes GaN HEMTs, LEDs, InGaAs HEMTs existing foundry processes. A modular process flow incorporated so devices can modeled design kit process, leverage much manufacturing infrastructure. initial focus on demonstration wafer-level with 0.18 μm 200 mm wafers, report progress made materials, circuit towards this goal.