Optimizing integrated circuit design through use of sequential timing information
作者： Ellen Sentovich , Andreas Kuehlmann , Roberto Passerone , Christoph Albrecht , Philip Chong
DOI:
关键词:
摘要: A method is provided that includes: determining a minimum clock cycle can be used to propagate signal about the critical in circuit design; wherein design has highest proportionality of delay number registers; for element design, sequential slack associated with element; represents from among respective maximum delays added structural cycles which constituent, based upon determined limit duration; using ascertain optimization flexibility throughout multiple stages flow.
lens.org 参考文章(37)
Andreas Kuehlmann, David Seibert, Sascha Richter, Christoph Albrecht, Optimization of combinational logic synthesis through clock latency scheduling ,(2006)
Robert E. Tarjan, Andrew V. Goldberg, Loukas Georgiadis, Renato F. Werneck, An experimental study of minimum mean cycle algorithms algorithm engineering and experimentation. pp. 1- 13 ,(2009)
Fumihiro Minami, Takashi Ishioka, Masami Murakata, Naohito Kojima, Method for distributing clock signals to flip-flop circuits ,(2002)
Hamid Savoj, Michael A. Riepe, Robert M. Swanson, Timothy M. Burks, Ginneken Lukas Van, Karen E. Vahtra, Method for generating design constraints for modulates in a hierarchical integrated circuit design system ,(2002)
Thomas Hughes, Cheng-Gang Kong, System and method for providing swap path voltage and temperature compensation ,(2006)
Robert Benjamin Gass, Method and apparatus for optimum transparent latch placement in a macro design ,(2003)
Liang-Fang Chao, Hsing-Mean Sha, Retiming and clock skew for synchronous systems international symposium on circuits and systems. ,vol. 1, pp. 283- 286 ,(1994) , 10.1109/ISCAS.1994.408810
A.P. Hurst, P. Chong, A. Kuehlmann, Physical placement driven by sequential timing analysis international conference on computer aided design. pp. 379- 386 ,(2004) , 10.1109/ICCAD.2004.1382605
Ivan S. Kourtev, Baris Taskin, Eby G. Friedman, Timing Optimization Through Clock Skew Scheduling ,(2008)
Joe G. Xi, Wayne W.-M. Dai, Useful-skew clock routing with gate sizing for low power design design automation conference. pp. 383- 388 ,(1996) , 10.1145/240518.240592