Merging eviction and fill buffers for cache line transactions
作者： Jeff Rupley , Tarun Nakra
DOI:
关键词:
摘要: A processor includes a first cache memory and bus unit in some embodiments. The plurality of buffers is operable to allocate selected buffer for fill request associated with line be stored memory, load data from the into buffer, transfer parallel storing eviction an evicted buffer.
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