A Fast Multiplierless Architecture for General Purpose VLSI FIR Digital Filters
作者： Imran Shah , Arup Bhattacharya
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摘要: A multiplierless algorithm for calculating the convolution of a Finite Impulse Response (FIR) digital filter is presented. The based on partial slicing input data vector words and performing in distributed fashion. fast, flexible hardware efficient architecture implementing described. Simulation results prototype one tap are presented, demonstrating high speed capability architecture.
sci-hub.se 参考文章(7)
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