Reduction of process antenna effects in integrated circuits
作者： Neeraj Dogra , Runip Gopisetty
DOI:
关键词:
摘要: An approach for reducing antenna effects in integrated circuits involves evaluating an circuit design to identify one or more problem interconnects that satisfy certain effect criteria. The are selectively connected discharge paths and the is updated reflect connections paths.
lens.org 参考文章(19)
Joe Ko, Chen-Chiu Hsue, Grounding method to eliminate the antenna effect in VLSI process ,(1993)
Bing-Yue Tsui, Conductive photoresist to mitigate antenna effect ,(1996)
Bill Hsu, Joe Ko, Method of making layout design to eliminate process antenna effect ,(1995)
Daniel Wesley Dulitz, Andrea Berens, Venkata K. R. Chiluvuri, Mohan Guruswamy, Srilata Raman, Robert L. Maziasz, Automatic synthesis of standard cell layouts ,(1996)
William George En, Process induced charging damage control device ,(1997)
Richard Allan Tuck, Hugh Edward Bishop, Field electron emission materials and devices ,(2002)
W. Maly, C. Ouyang, S. Ghosh, S. Maturi, Detection of an antenna effect in VLSI designs defect and fault tolerance in vlsi and nanotechnology systems. pp. 86- 94 ,(1996) , 10.1109/DFTVS.1996.571999
Mohankumar Guruswamy, Srilata Raman, Robert L. Maziasz, Andrea Fernandez, Daniel Wesley Dulitz, Method of routing an integrated circuit ,(1996)
Hung-Der Su, Di-Son Kuo, Jian-Hsing Lee, Test structures for monitoring gate oxide defect densities and the plasma antenna effect ,(1997)
C. C. Chen, S.-L. Chow, The Layout Synthesizer: An Automatic Netlist-to-Layout System design automation conference. pp. 232- 238 ,(1989) , 10.1145/74382.74422