Pipelined read architecture for memory
作者： Sachidanandan Sambandan , Phillip M. L. Kwong , Duane R. Mills
DOI:
关键词:
摘要: A memory device having a array is described. The has sensing stage to sense data stored within the array. also an output that been sensed by stage. and are separated so associated with first address can be while second output.
google.co.in 参考文章(11)
Loren L. McLaury, Pipelined SAM register serial output ,(1991)
Brian Dipert, Markus Levy, Designing with flash memory : the definitive guide to designing flash memory hardware and software for components and PCMCIA cards Annabooks. ,(1993)
Eliyahou Harari, Sanjay Mehrotra, Robert D. Norman, Flash EEprom system ,(1990)
B. Prince, Memory in the fast lane IEEE Spectrum. ,vol. 31, pp. 38- 41 ,(1994) , 10.1109/6.259491
Junichi Miyamoto, Semiconductor memory device having serial access mode ,(1992)
Ching-Shi Jenq, Ping Wang, Floating gate memory array with latches having improved immunity to write disturbance, and with storage latches ,(1992)
Mark S. Myers, Atiq Bajwa, Sunil Shenoy, Robert Duzett, M. Vittal Kini, Kent Mason, Programmable memory array control signals ,(1987)
Sachidanandan Sambandan, Kerry Tedrow, David A. Leak, Address transition detection noise filter in pulse summation circuit for nonvolatile semiconductor memory ,(1992)
Hiroshi Iwahashi, Semiconductor memory device with plural latches for read out ,(1985)
Junichi Shikatani, Kazuyoshi Unno, Takashi Maki, Semiconductor storage device having latch circuitry coupled to data lines for eliminating through-current in sense amplifier ,(1994)