[multi-gate dram with deep-trench capacitor and fabrication thereof]

摘要: A multi-gate DRAM cell is described, including a transistor and deep trench capacitor. The includes semiconductor pillar, multi-gate, gate dielectric layer, first second source/drain regions. pillar beside the capacitor not overlapping with latter. at least on three sidewalls of separated by can be treble or surrounding gate. region in top portion coupling