Software-directed Cache Management in Multiprocessors

摘要: We discuss three different software-assisted cache coherence enforcement schemes for large shared-memory multiprocessor systems using interconnection networks. All rely on a compiler to detect potential problems and generate code enforce in parallel program. The main goals are maintain without any interprocessor communication keep overhead low. former is achieved by compile-time knowledge of the parallelism data dependences latter special hardware invalidate stale blocks time independent number such blocks. Cache words allowed become inconsistent with memory as long decided it safe do so. This allows invalidation be delayed beyond new copy word has been generated till invalidated. differ complexity power detection algorithms, additional hardware, run-time support provides deciding what invalidate. Each scheme improves over previous one terms amount unnecessary achieves higher hit ratios.