System and method for on-chip-variation analysis
作者： Yuan-Te Hou , Lee-Chung Lu , Chung-Hsing Wang
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摘要: Apparatus is provided for performing timing analysis on a circuit. A first storage device portion stores state dependent stage weight each of rising time arc and falling plurality cells in cell library. An adder calculating sum the weights that are included circuit path. second table containing chip variation (OCV) derating factors. The indexed by values sum. total path delay calculated path, based OCV factor corresponding to
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