100 Gbit/s Fully Integrated InP DHBT-Based CDR/1:2 DEMUX IC
作者： R. E. Makon , R. Driad , R. Losch , J. Rosenzweig , M. Schlechtweg
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摘要: In this paper, a 100 Gbit/s fully integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX) is presented. The (IC) realized using an in-house InP double heterostructure bipolar transistor (DHBT) technology exhibiting cut-off frequency values of more than 300 GHz for both fT fmax. CDR IC consists mainly half-rate linear phase detector including DEMUX, loop filter, voltage controlled oscillator (VCO). A signal at the corresponding input gives rise to 50 recovered demultiplexed output featuring clear eye opening swing 500 mVpp. extracted from features 250 mVpp, while peak-to-peak (pp) rms jitter amount 2.1 ps 0.5 ps, respectively. full dissipates W single supply -4.5 V.
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