A 10-b 70-MS/s CMOS D/A converter
作者： Y. Nakamura , T. Miki , A. Maeda , H. Kondoh , N. Yazawa
DOI: 10.1109/4.75066
关键词:
摘要: A 10-b 70-MS/s CMOS D/A converter fabricated in a 1- mu m technology is described. An integral linearity error caused by distributions of current sources reduced new switching sequence called hierarchical symmetrical switching. differential an off-axis drain-source implantation the layout technique sources. The using single-polycide double-metal standard digital process. Both and errors are less than +or-0.5 LSB. settling time to +or-0.1 % 14 ns. worst-case glitch energy approximately 60 pV-s. This has single power supply 5 V dissipates 170 mW at 70 MS/s. chip size 2.02 mm*1.87 mm. >
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sci-hub.se 参考文章(3)
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