Analysis of the parasitic S/D resistance in multiple-gate FETs
作者： A. Dixit , A. Kottantharayil , N. Collaert , M. Goodwin , M. Jurczak
关键词:
摘要: The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from high parasitic resistance due to narrow width of their source/drain (S/D) regions. We analyze S/D behavior FETs using novel, geometry-based analytical model, which validated three-dimensional simulations and experimental results. model predicts limits scaling, reveal that contact between silicide Si-fin dominates FETs. It shown selective epitaxial growth Si on regions alone may be insufficient meet semiconductor roadmap target at
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