Low Complexity Flexible Hardware Efficient Decimation Selector
作者： V. Rakesh , K.G. Smitha , A.P. Vinod
DOI: 10.1109/ISED.2011.18
关键词:
摘要: Coefficient decimation (CD) is a computationally efficient reconfigurable finite impulse response (FIR) filter method. Reconfigurability achieved by decimating the fixed coefficient modal (prototype) in-order to realize variable bandwidth responses. Reconfigurable selector vital part of CD architecture which allows user select different factor choice. In this paper, we propose low complexity, hardware for selector. The implementation results in Virtex IV-xc4vsx35-10ff668 FPGA shows that when compared other techniques available literature, proposed technique saves up 5.2% area and 7.6% power order 101.
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