DOI: 10.1109/PIMRC.2006.254336
关键词:
摘要: The most computationally demanding block of a software defined radio (SDR) receiver is the channelizer which operates at highest sampling rate. Reconfigurability and low complexity are two key requirements SDR channelizers. Two new reconfigurable architectures finite impulse response (FIR) filters for channelizers proposed in this paper. Our methods based on binary common subexpression elimination (BCSE) algorithm. capable operating high speed clock frequency 109.7 MHz Xilinx's Virtex II 2v2000ff896-6 FPGA 12-bit FIR filter coefficient. Design examples show that our method offers an average reduction 23% number addition operations compared to conventional implementations.