Bit line setup and discharge circuit for programming non-volatile memory

摘要: A NAND EEPROM having a shielded bit line architecture reduces supply voltage and ground noise resulting from charging or discharging lines. The has PMOS pull-up transistor an NMOS pull down connected to virtual power node. control circuit for lines controls the gate of limit peak current when via In particular, operates in non-saturation mode current. One such creates mirror applies reference voltages. programming method sets up by pre-charging unselected controlled while latches circuitry charge discharge selected according respective data bits being stored. Another setup includes two stages. first stage pre-charges all pull-up, second uses leave charged depending on voltages transistors can be reduce caused through latches.