作者: Pradipta K Nayak , Jesus A Caraveo‐Frescas , Zhenwei Wang , Mohamed N Hedhili , Husam N Alshareef
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摘要: DOI: 10.1002/aelm.201500014 Figure 1 a shows the process-fl ow for fabrication of IZO TFTs. The TFTs with fi lms that were immersed in DIW prior to nal crystallization at 250 °C are henceforth referred as DIW-treated and not untreated b schematic device structure c top-view image an actual obtained by 3D optical surface profi ler (NewView 7300, Zygo). output characteristics shown d,e, respectively. Transfer f. All work low operating voltage range due spin coated AlO x dielectric having high capacitance ca. 151 nF cm −2 measured Hz (Figure S1, Supporting Information). Untreated exhibited average μ FE ~8.6 ± 0.9 2 V −1 s drain on-current off-current ratio ( I on / off ) 10 4 –10 5 . Interestingly, higher (>10 6 maximum peak 51 , which is six times than dual sweep transfer curve showed very negligible hysteresis difference 0.02 between forward backward S2, No signifi cant was observed varying channel width length (W/L) from (W = 500 μm, L 100, 75, 50 μm). sub-threshold swing SS value found be 0.189 0.016 dec 0.102 0.012 Reproducibility similar performance checked repeated experiments. statistics TFT parameters different experiments listed Table Information, corresponding curves S3, Information. These results represent highest eld-effect mobility among solution-processed using patterned metal oxide layers. Positive gate-bias stress (PBS) negative (NBS) stability tests carried out, especially DIWtreated PBS left panel g. A bias +/−1 applied gate terminal during PBS/NBS while source xed 0 V. Parallel shifting positive direction increasing duration. threshold shift +0.3 after 100 no further increase duration up 3000 s. Similar NBS S4a, under change Transparent based thin lm transistors (TFTs) have been extensively studied last decade their potential application displays other electronic devices. [ ]