Three-dimensional integrated capacitance structure

摘要: A three-dimensional integrated capacitance structure comprises at least two arrays of “unit cells” on respective layers an IC, with each unit cell comprising a center conductor and conducting ring which surrounds the conductor. Each array plurality cells, tiled given IC layer predetermined pitch. The are arranged vertically such that adjacent vertical offset in x y dimensions by fraction—preferably ½—of cells' includes vias to interconnect is connected immediately above and/or below conductor, ring.