Online Estimation of Architectural Vulnerability Factor for Soft Errors

摘要: As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior research shown that there is significant architecture-level masking, many solutions take advantage of this effect. work also thatthe degree such masking can vary significantly across workloads between individual workload phases, motivating dynamic adaptation optimal cost benefit. For adaptation, it be able accurately estimate amount ofmasking or architecture vulnerability factor (AVF) online, while program running. Unfortunately, existing estimating AVF often based offline simulators hard implement in real This paper proposes a novel way using simple modifications processor. The estimation method applies both logic storage structures Compared previous methodsfor AVF, our does not require any simulation calibration different workloads. We tested with widely used simulator from industry, four processor 100 200 intervals each eleven SPEC benchmarks. results show provides acceptably accurate estimates at runtime. absoluteerror rarely exceeds 0.08 all application structures, mean absolute given structure combination always within 0.05.