A novel stack capacitor cell for high density FeRAM compatible with CMOS logic

作者: T. Hayashi , Y. Igarashi , D. Inomata , T. Ichimori , T. Mitsuhashi

DOI: 10.1109/IEDM.2002.1175899

关键词:

摘要: We have developed 4 Mb 1T1C FeRAM device technology using 0.25 /spl mu/m design rules, which is fully compatible with CMOS logic. This consists of three key technologies: a diffusion barrier and an oxidation to W-plug, low thermal budget process for SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT)-capacitors no via contact cell scheme.

参考文章(2)
B. Yang, Y.M. Kang, S.S. Lee, K.H. Noh, N.K. Kim, S.J. Yeom, N.S. Kang, H.G. Yoon, Highly reliable 1 Mbit ferroelectric memories with newly developed BLT thin films and steady integration schemes international electron devices meeting. ,(2001) , 10.1109/IEDM.2001.979633
T. Yamazaki, K.-i. Inoue, H. Miyazawa, M. Nakamura, N. Sashida, R. Satomi, A. Kerry, Y. Katoh, H. Noshiro, K. Takai, R. Shinohara, C. Ohno, T. Nakajima, Y. Furumura, S. Kawamura, Advanced 0.5 /spl mu/m FRAM device technology with full compatibility of half-micron CMOS logic device international electron devices meeting. pp. 613- 616 ,(1997) , 10.1109/IEDM.1997.650459