作者: T. Hayashi , Y. Igarashi , D. Inomata , T. Ichimori , T. Mitsuhashi
DOI: 10.1109/IEDM.2002.1175899
关键词:
摘要: We have developed 4 Mb 1T1C FeRAM device technology using 0.25 /spl mu/m design rules, which is fully compatible with CMOS logic. This consists of three key technologies: a diffusion barrier and an oxidation to W-plug, low thermal budget process for SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT)-capacitors no via contact cell scheme.