作者: J.-H. Kim , D. J. Jung , Y. M. Kang , H. H. Kim , W. W. Jung
DOI: 10.1109/RELPHY.2007.369950
关键词:
摘要: 64 Mb FRAM with 1T1C (one-transistor and one-capacitor) cell architecture has progressed greatly for a robust level of reliability. Random-single-bits appeared from package-level tests are attributed mostly to extrinsic origins (e.g. interconnection failures) rather than intrinsic ones. The failures can be linked two activation energies: while one is 0.27 eV originated oxygen-vacancy movements at the top interface grain boundary in ferroelectric films, other 0.86 caused by imperfection either top-electrode contact (TEC), or bottom-electrode (BEC), both, capacitor. As result applying novel schemes remove analyzed defectives, we have no bit failure up 1000 hours over both high-temperature-operating-life (HTOL) high-temperature-storage (HTS)