AES on FPGA from the fastest to the smallest
作者： Tim Good , Mohammed Benaissa
DOI: 10.1007/11545262_31
关键词:
摘要: Two new FPGA designs for the Advanced Encryption Standard (AES) are presented. The first is believed to be fastest, achieving 25 Gbps throughput using a Xilinx Spartan-III (XC3S2000) device. second smallest and fits into Spartan-II (XC2S15) device, only requiring two block memories 124 slices achieve of 2.2 Mbps. These show extremes what possible have radically different applications from high performance e-commerce IPsec servers low power mobile home applications. speed design presented here includes support continued during key changes both encryption decryption which previous pipelined omitted.
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sci-hub.st 参考文章(13)
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