Method of scavenging impurities in forming a gate stack having an interfacial layer
作者： Clement Hsingjen Wann , Yasutoshi Okuno , Liang-Gi Yao , Kuan-Ting Liu
DOI:
关键词:
摘要: A multi-layer scavenging metal gate stack, and methods of manufacturing the same, are disclosed. In an example, a stack disposed over semiconductor substrate includes interfacial dielectric layer substrate, high-k layer, first conductive second layer. The third material that scavenges oxygen impurities from adsorbs prevents diffusing into
lens.org 参考文章(7)
Sung Kee Han, Jung Min Park, Jong Ho Lee, Hyung Suk Jung, Ju Youn Kim, Cmos semiconductor devices having dual work function metal gate stacks ,(2006)
Vijay Narayanan, Takashi Ando, Martin M. Frank, Changhwan Choi, Unoh Kwon, Low Threshold Voltage And Inversion Oxide Thickness Scaling For A High-K Metal Gate P-Type MOSFET ,(2012)
Vijay Narayanan, Takashi Ando, Inversion thickness reduction in high-k gate stacks formed by replacement gate processes ,(2012)
Paul C. Jamison, Vamsi K. Paruchuri, Vijay Narayanan, Takashi Ando, Sufi Zafar, Hemanth Jagannathan, Changhwan Choi, Lisa F. Edge, Structure and method to obtain EOT scaled dielectric stacks ,(2015)
Vijay Narayanan, Takashi Ando, Martin M. Frank, Changhwan Choi, Scavanging metal stack for a high-k gate dielectric ,(2012)
Eduard A. Cartier, Vamsi K. Paruchuri, Bruce B. Doris, Vijay Narayanan, Keith Kwong Hon Wong, Matthew W. Copel, Rajarao Jammy, Young-Hee Kim, Barry P. Linder, Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled cmos devices ,(2006)
Wen-Chih Yang, Chien-Liang Chen, Chii-Horng Lee, Harry Chuang, Semiconductor device with high-K/dual metal gate ,(2007)