Digital data processor for matrix-vector multiplication
作者： Jeremy S. Ward
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摘要: A digital data processor for matrix-vector multiplication is provided, and comprises a systolic array (10) of bit-level, synchronously clock activated processing cells (12) each connected to its row column neighbours. On cycle, cell multiplies an input bit respective vector coefficient by matrix equal +1, -1 or 0, adds it cumulative sum carry bits. Input bits pass along rows through one per cycle. Contributions product are accumulated in columns. output from the bit-serial, word parallel, Isb leading, temporally skewed. Transforms such as discrete Fourier transform may be implemented two-channel device (150), which channel contains two processors invention with intervening serial multiplier. Processors replicated implement multuplication larger matrices.
google.de 参考文章(9)
Charles E. Leiserson, Hsiang-Tsung Kung, Systolic array apparatuses for matrix computations ,(1983)
Bahram Alizadeh Parvin, Systolic array for solving cyclic loop dependent algorithms ,(1985)
John V. McCanny, John G. McWhirter, Digital data processor incorporating an orthogonally connected logic cell array ,(1985)
S. Winograd, On computing the discrete Fourier transform Mathematics of Computation. ,vol. 32, pp. 175- 199 ,(1978) , 10.1090/S0025-5718-1978-0468306-4
R. Lyon, Two's Complement Pipeline Multipliers IEEE Transactions on Communications. ,vol. 24, pp. 418- 425 ,(1976) , 10.1109/TCOM.1976.1093315
Kenneth William Wood, John Graham Mcwhirter, Digital data processor for multiplying data elements by coefficients ,(1984)
Kenneth William Wood, John Vincent Mccanny, John Graham Mcwhirter, Integrated data processing circuits ,(1982)
Mccanny John Vincent, Mcwhirter John Graham, Wood Kenneth William, A digital data processor for matrix/matrix multiplication ,(1985)
Mccanny John Vincent, Mcwhirter John Graham, Wood Kenneth William, DIGITAL DATA PROCESSOR ,(1983)